Content Addressable Memories (CAMs) are commonly used in cache systems, and other address translation systems, of high speed computing systems. They are also useful in high-speed network routers, and many other applications known in the art of computing. CAMs can be Binary (logic states, zero and one) or Ternary (logic states zero, one and don't care).
A CAM system is composed of CAM blocks with arrays of CAM cells. A CAM system typically has a CAM block array (M×N) that includes a plurality of rows (M) and a plurality of columns (N). Further, each row has a plurality of CAM blocks, and each CAM block has a plurality of CAM cells. These arrays typically have vertically running bit lines and search lines for data read/write function and horizontal running word lines and match lines. All CAM cells in a column share the same bit lines and search lines, whereas, the word lines and match lines are shared by all cells in a row. Each CAM cell includes a pair of memory elements and a corresponding pair of compare circuits.
The CAM cells are characterized by circuitry, capable of generating a match output for each row of CAM blocks in the CAM cell, thereby indicating whether any location of the array contains a data pattern that matches a query input and the identity of that location. Each CAM cell typically has the ability to store a unit of data, and the ability to compare that unit of data with a unit of query input and each CAM block has the ability to generate a match output. In parallel data search, an input keyword is placed at the search bit lines after precharging the match lines to a power supply voltage Vdd.
The data in each CAM cell connected to a match line is compared with this data, and if there is a mismatch in any cell connected to a match line, the match line will discharge to ground through the compare circuit of that CAM cell. A compare result indication of each CAM block in a row is combined to produce a match signal for the row to indicate whether the row of CAM cells contains a stored word, matching a query input. The match signals from each row in the CAM cell together constitute match output signals of the array, and these signals may be encoded to generate the address of matched locations or used to select data from rows of additional memory.
Each CAM cell in each column is typically connected to a common read/write bit line pair and search bit line pair. The common read/write bit line is used to write the data to a pair of memory cells, which can be a part of a CAM cell. Each memory cell is accessed using a word line which is decoded using an input address. The common read/write bit line is also used for reading the data from a memory cell. The differential developed across the read/write bit lines are sensed using a sense amplifier during a read cycle.
Further, each CAM cell in each column is typically connected to a common query data line, also referred to as a common search bit line. The common search bit line enables simultaneous data searching in each CAM cell in a column from a query input. The common search data line can also be used as a write data line, when the CAM cell is based on a PMOS compare circuit.
Each CAM cell in each column of a CAM array is typically connected to a common read/write bit line and a search bit line. The common read/write bit line is used to write the data to a pair of memory cells, which can be part of a single memory cell, such as a binary CAM. Each memory cell is accessed using a word line which is decoded using an input address. The common read/write bit line is also used for reading the data from a memory cell. The differential developed across the read/write bit lines are sensed using a sense amplifier during a read cycle.
Further, each CAM cell in each column in the CAM arrays is typically connected to a common query data line, also referred to as a common search data line. The common search data line enables simultaneous data searching in each CAM cell in a column from a query input. The common search data line can also be used as a write data line, when the CAM array is based on a PMOS compare circuit.
The unit of data that is stored in a BINARY cell is binary, having two possible states: logic one, and logic zero. To store these two states, two memory elements are needed. CAM blocks of these binary CAM cells produce a local match compare result if the query input is equal to the data stored in the CAM cells in the CAM blocks, the query input contains a don't care state, or the data stored is a don't care data. The CAM cells produce a mismatch result otherwise. The CAM cells are particularly useful in address translation systems that allow variable sized allocation units.
During normal operation of a CAM, whenever data is searched, and if there is a hit HT during one clock cycle, all contents of the TCAM cell are searched and if the number of matches is more than one, the multi hit flag MH is raised, which signifies that there are more than one hits in the CAM system. In case of a multi hit match, the multibit address LSB gives out LSB HA as output. Conventionally, in a CAM array, at a given time, one clock cycle is used for performing each of the reading and writing operations. This CAM is also referred to as a one port or single port, denoting that a single clock cycle is used while performing a single function of operation of the CAM. Generally, current CAM arrays cannot perform more than one operation, i.e., search, write, and/or valid bit reset operations in a given clock cycle.